Joint Test Action Group (JTAG) is the common name for what was later standarized as the IEEE
1149.1 Standard Test Access Port and Boundary-Scan Architecture
- TDI (Test Data In)
- TDO (Test Data Out)
- TCK (Test Clock)
- TMS (Test Mode Select)
- TRST (Test Reset) optional.
2．JTAG Application for CPLD/FPGA:
Application of JTAG for CPLD/FPGA is allowing device programmer hardware to transfer data
into internal non-volatile device memory (CPLDs). Some device programmers serve a double
purpose for programming as well as debugging the device. In the case of FPGAs, volatile memory
devices can also be programmed via the JTAG port normally during development work. In
addition, newer parts, for instance Xilinx Virtex-5, have internal monitoring capability accessible
via the JTAG port.
3.CPLD/FPGAs software and hardware developing for function test:
- Developing different hardware to match testing different part.
- Developing program for testing CPLD/FPGA with HDL(Hardware Description Language),and compile the program to generate assembler that is a device programming files. Load device programming files into internal device memory using JTAG device programmer hardware.
4.What testing we can do:
- Check the JTAG ID CODE, All CPLD/FPGA have a JTAG ID CODE.
- Check the Part Number, can read the part number from CPLD/FPGA via JTAG.
- Functional testing, can check the LUT, CLB, Memory, PLL, IO pins:
5. Successful Case of FPGA (EP1C12F256)
a. Hard ware:
b. PCB Layout
c. RTL after compiling
d. Check JTAG ID and Part Number, Load program, Function test.